This is the SVERICL Research Inc. flagship.
The goal of (svericl) is:
To implement SystemVerilog, in its entirety,
as an embedded Domain-Specific Language,
inside a powerful host language.
Fortunately, along the way, there are highly-useful by-products of even modest subsets of the full functionality.
Initial development efforts are focused on a particularly fertile subset of functionality, to yield tools related to syntactic abstraction, code-generation, code-formatting, and even support for other tools through an extensible pre-processor.
It will see an initial public release in 2022.